1. Field of the Invention
This invention generally relates to an integrated circuit device, and in particular to a logic integrated circuit device for outputting a desired output selectively.
2. Description of the Prior Art
FIGS. 2a and 2b, when combined as shown in FIG. 2, illustrate a prior art logic integrated circuit device comprised of a programmable logic device (PLD). The illustrated logic integrated circuit device includes a logic circuit 4a comprised of an OR gate OR, an exclusive OR gate XOR, three gate switches GS11 through GS13 and inverters INV11 through INV13. In this logic circuit 4a, an input terminal 11 to which a logic signal a is input is connected to a first input terminal of the OR gate OR, to a first input terminal of the exclusive OR gate XOR and also to an output terminal 13 through the gate switch GS11. And, an input terminal 12 to which a logic signal b is input is connected to a second input terminal of the OR gate OR and also to a second input terminal of the exclusive OR gate OR. The output terminal of the OR gate OR is connected to the output terminl 13 through the gate switch GS12 and the output terminal of the exclusive OR gate XOR is connected to the output terminal 13 through the gate switch GS13.
Logic signals p, q and r for controlling the gate switches GS11, GS12 and GS13 of the logic circuit 4a are output from output terminals of three AND gates AND1, AND2 and AND3 of a switch control circuit 5a, respectively. The output terminals of these AND gates AND1, AND2 and AND3 are connected to positive control signal input terminals of the gate switches GS11, GS12 and GS13 of the logic circuit 4a, respectively, and also to negative control signal input terminals of the gate switches GS11, GS12 and GS13 through inverters INV11, INV12 and INV13, respectively. When a H level logic signal of a predetermined positive d.c. voltage has been input into the positive control signal input terminal and at the same time a L level logic signal of ground voltage has been input into the negative control signal input terminal, the gate switches GS11, GS12 and GS13 are turned on; whereas, when a L level logic signal has been input into the positive control signal input terminal and at the same time a H level logic signal has been input into the negative control signal input terminal, the gate switches GS11, GS12 and GS13 are turned off.
There is also provided a logic circuit 4b which is constructed similarly with the above-described logic circuit 4a, and the logic circuit 4b includes a pair of input terminals 11 and 12 and an output terminal 14. In the logic circuit 4b, the input terminal 12 to which a logic signal b is input is connected to the first input terminal of each of OR gate OR and exclusive OR gate XOR and also to the output terminal 14 through the gate switch GS11, whereas the input terminal 11 to which a logic signal a is input is connected to the second input terminal of of each of OR gate OR and exclusive OR gate XOR. It is to be noted that logic signals output from the output terminals 13 and 14 of the logic circuits 4a and 4b are designated by A and B.
Also provided in the structure shown in FIGS. 2a and 2b include a pair of EPROM data read out circuits of identical structure. The data read out circuit 2a includes four MOSFETs and two floating gate type MOSFETs (FAMOSFETs). In the data read out circuit 2a, the drain of a P-channel MOSFET Q1 is connected to a d.c. power supply voltage V.sub.cc and this P-channel MOSFET Q1 has its gate connected to ground and its source connected to the gate and also to the drain of an N-channel MOSFET Q2. The gate of FAMOSFET Q3 is connected to a data input terminal 21a and the FAMOSFET Q3 has its source connected to ground and its drain connected to the source of MOSFET Q2 and also to the input terminal of inverter INV21 of the switch control circuit 5a. In addition, MOSFETs Q4 and Q5 and FAMOSFET Q3 are connected similarly with MOSFETs Q1 and Q2 and FAMOSFET Q3, and there is also provided a FAMOSFET Q6 which has its gate connected to a data input terminal 22a and its drain connected to the input terminal of inverter INV22 of the switch control circuit 5a. Logic signals output from the drains of FAMOSFET Q3 and Q6 of the data read out circuit 2a to the switch control circuit 5a are designated by s and t. It should also be noted that the data read out circuit 2b is constructed as connected similarly with the data read out circuit 2a.
With the data read out circuits 2a and 2b as constructed above, when a data write in voltage of a sufficiently large voltage, e.g., .+-.13.5 V, as compared with d.c. power supply voltage V.sub.cc, is input into FAMOSFETs Q4 and Q6 through the input terminals 21a and 21b, these FAMOSFETs Q3 and Q6 are programmed and thus maintained off and the drain voltage of each of FAMOSFETs Q3 and Q6 becomes H level. Thus, the data read out circuits 2a and 2b output logic signals s and t of H level. On the other hand, if the write in voltage is not input into FAMOSFETs Q3 and Q6, these FAMOSFETs Q3 and Q6 are not programmed and each of FAMOSFETs Q3 and Q6 changes its state from an off state to an on state in accordance with a word line selection signal (not shown) of H level applied to the gate of each of FAMOSFETs Q3 and Q6, whereby the drain of each of FAMOSFETs Q3 and Q6 is set to L level of ground voltage. Thus, the data read out circuits 2a and 2b output logic signals s and t of L level.
The switch control circuit 5a includes four inverters INV21, INV22, INV23 and INV24 and three AND gates AND1, AND2 and AND3. In the switch control circuit 5a, the output terminal of inverter INV21 is connected to a first input terminal of each of AND gates AND1 and AND3 and also to a first input terminal of AND gate AND2 through inverter INV23. In addition, the output terminal of inverter INV22 is connected to a second input terminal of each of AND gates AND1 and AND2 and also to a second input terminal of AND gate AND3 through inverter INV24. Logic signals p, q and r output from output terminals of AND gates AND1, AND2 and AND3 are supplied to the positive control signal input terminals of gate switches GS11, GS12 and GS13, respectively, as control signals of gate switches GS11, GS12 and GS13 of the logic circuit 4a as described above. It should be noted that the switch control circuit 5b is constructed as connected similarly with the above-described switch control circuit 5a.
With the logic integrated circuit device constructed as described above, logic signals s and t output corresponding to the data set by the data read out circuits 2a and 2b are input into the corresponding switch control circuits 5a and 5b which, in response thereto, output switch control logic signals p, q and r to the respective control signal input terminals of gate switches GS11, GS12 and GS13 of the logic circuits 4a and 4b. In this case, in accordance with the signal level of each of the switch control logic signals p, q and r, the respective gate switches GS11, GS12 and GS13 are turned on or off, whereby the pair of logic circuits 4a and 4b outputs an input logic signal a or b, a logical sum signal a+b, or an exclusive logical sum signal a.sym.b. Tables 1 and 2 are tables showing the relationship between each logic signal and an input/output logic signal for the switch control operation of the structure shown in FIGS. 2a and 2b.
In the above-described prior art logic integrated circuit device, three kinds of output signals may be selectively output from each of the output terminals 13 and 14 as described above depending on whether a data is written in FAMOSFETs Q3 and Q6 of the data read out circuits 2a and 2b or not. However, there is virtually no chance to use a combination of two logical sum outputs or two exclusive logical sum outputs due to the structure of the logic circuit, so that the OR gate, the exclusive OR gate and the gate switches which are not in use are redundant and they occupy an unnecessary area in the chip.